(a) Field of the Invention
The present invention relates to a BGA type semiconductor device having a solder-flow damping/stopping pattern and a method for manufacturing the same. More specifically, the present invention relates to a BGA type semiconductor device including an interconnect pattern having a function for damping/stopping solder flow instead of forming a solder resist layer, and to a manufacturing method thereof having a reduced process steps.
(b) Description of the Related Art
There are constantly strong demands for more fine-patterned and integrated semiconductor devices for obtaining smaller, lighter, faster, electronic equipment with increased functions. However, it becomes increasingly difficult to meet such demands simply by increasing the number of pins of the semiconductor chips, for example. In recent years, instead of the pin type semiconductor devices, ball grid array (hereinafter, referred to as BGA) type semiconductor devices have drawn larger attention.
Referring now to FIGS. 1 to 3, the structure of the BGA type semiconductor device is described below. FIG. 1 is a top plan view of a BGA type semiconductor device as viewed from the bottom surface of an interposing substrate 12, illustrating a semiconductor chip 14 mounted on a top surface of the interposing substrate 12 by a dotted line. FIG. 2 is an enlarged partial view of the interconnect pattern shown in FIG. 1. FIG. 3 is a combined sectional view which shows the combination of the sectional views taken along line Ixe2x80x94I and line IIxe2x80x94II in FIG. 1, illustrating the locational relationship in the sectional view of the semiconductor device between the semiconductor chip 14 and the solder balls 17.
As shown in FIGS. 1 to 3, the BGA type semiconductor device 10 is composed of the interposing substrate or interposer substrate 12, the semiconductor chip 14 die-bonded onto the top surface of the interposing substrate 12, and an encapsulating resin layer 15 which encapsulates therein the semiconductor chip 14 on the interposing substrate 12 together with the bonding wires not shown in the drawing.
The interposing substrate 12 has, on its bottom surface at which the interposer substrate 12 is mounted by a printed circuit board, a bottom interconnect pattern 16 which is electrically connected to the chip electrodes of the semiconductor chip 14 through the top interconnect pattern, and a plurality of solder balls 17 that are attached to respective solder ball islands (not shown) connected to the bottom interconnect pattern 16. During the process of surface-mounting the semiconductor device 10 on the printed circuit board, the solder balls 17 are melted together with respective solder bumps formed on the printed circuit board and thereby form respective bonding parts.
The encapsulating resin layer 15 encapsulates therein the semiconductor chip 14, and the chip electrodes (not shown) of the semiconductor chip 14 are electrically connected to the bottom interconnect pattern 16 on the interposing substrate 12. The bonding parts of the solder balls 17 are reinforced by a reinforcing resin 18.
The bottom interconnect pattern 16 is electrically connected through the interposing substrate 12 with a top interconnect pattern (not shown) which is bonded via gold wires to the chip electrodes of the semiconductor chip 14 mounted on the top surface of the interposing substrate 12. As shown in FIG. 2, the bottom interconnect pattern 16 is connected to the solder ball islands (19) and connects the solder balls 17 to the chip electrodes of the semiconductor chip 14 in the shortest possible distance on the bottom surface of the interposing substrate 12.
Referring now to FIGS. 4A to 4G, the process for manufacturing a conventional BGA type semiconductor device such as shown in FIG. 1 will be described below. The reference numerals for the constituent elements in FIGS. 4A to 4G are differentiated from those in FIGS. 1 to 3 for avoiding a confusion.
First, as shown in FIG. 4A, for starting fabrication of the BGA type semiconductor device 10, a die pad 22 and a top interconnect pattern 24 is formed on the top surface of the interpose substrate 28 onto which a semiconductor chip is to be mounted. At the same time, a bottom interconnect pattern, which is similar to the bottom interconnect pattern 16 in FIG. 7 and not shown in FIG. 9, is formed on the bottom surface of the interposing substrate 28. The bottom interconnect pattern 26 is connected to the top interconnect pattern 24 through via holes in the interposing substrate 28. Solder ball islands 26 formed on the bottom surface of the interposer substrate 28 are connected to the bottom interconnect pattern similarly to the island 19 shown in FIG. 2.
The thickness of the interposing substrate 28 is at least 50 xcexcm and 100 xcexcm at its maximum. The interposing substrate 28, which is a rigid plate in this example, may be a flexible tape instead. The die pad 22, the top interconnect pattern 24, and the solder ball islands 26 may be formed on the same side of the interposing substrate 28 in a single layer.
Next, as shown in FIG. 4B, the entire top and bottom surfaces of the interposing substrate 28 are coated with a 5-xcexcm-thick solder resist layer 30.
Then, as shown in FIG. 4C, the solder resist layer 30 formed on the die pad 22, the bottom interconnect pattern 24 and the solder ball islands 26 is selectively removed to expose them through the solder resist layer 30.
In the next step, as shown in FIG. 4D, gold (Au) plating technique is applied to form a gold (Au) plating layer 32 on the exposed die pad 22, interconnect pattern 24 and solder ball islands 26.
Then, as shown in FIG. 4E, a semiconductor chip 36 is fixed onto the die pad 22 by using a mounting agent 34 made of an epoxy resin adhesive or the like. Subsequently, each chip electrode 40 of the semiconductor chip 36 is bonded with a corresponding interconnect of the top interconnect pattern 24 by using a gold (Au) wire 38.
Next, as shown in FIG. 4F, the semiconductor chip 36, the gold wires 38, and the top interconnect pattern 24 are encapsulated in an encapsulating resin layer 42. A plurality of solder balls 44 are then mounted on the respective solder ball islands 26 and then melted to form bonding parts.
The solder resist layer 30 is formed in the vicinity of the solder ball islands 26, covering the bottom interconnect pattern 16, to prevent molten solder from flowing onto the bottom interconnect pattern 16, as shown in FIG. 5, when the mounted solder balls are melted.
Next, as shown in FIG. 4G, epoxy resin is coated onto the base of the solder balls 44 to form a reinforcement resin layer 46 to enhance the bonding strength of the solder balls 44, whereby the BGA type semiconductor device 20 is obtained.
In the above conventional BGA type semiconductor device, it is necessary that the solder resist layer 30 block the flow of molten solder when the solder balls 44 are melted on the solder ball islands 26.
Namely, when the solder balls 44 are mounted and melted in a re-flow furnace, the solder resist layer 30 is formed to block the flow of molten solder. Therefore, the process of coating a solder resist layer 30 is important for blocking the molten solder ball 44. In addition, after the solder resist coating process and the subsequent melting process, the process of removing the solder resist layer 20 is also necessary to expose the die pad 22, the interconnect pattern 24 and the solder ball islands 26. The process for forming and removing the solder resist layer 30 complicates the manufacturing process for the semiconductor device.
It is therefore an object of the present invention to provide a BGA type semiconductor device having a solder-flow damping/stopping structure, instead of the solder resist layer, to simplify the manufacturing process for the semiconductor device.